On Optimization of Manufacturing of a Two-level Current-mode Logic Gates in a Multiplexer On Optimization of Manufacturing of a Two-level Current-mode Logic Gates in a Multiplexer

Abstract

In this paper, we introduce an approach to increase the density of field-effect transistors framework a two-level current-mode logic gates in a multiplexer. Framework the approach we consider manufacturing the inverter in heterostructure with the specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation. After that, dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease the value of mismatch-induced stress in the considered heterostructure. We introduce an analytical approach to analyze mass and heat transport in heterostructures during the manufacturing of integrated circuits with account mismatch-induced stress.